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FEATURES 5-Bit Digitally Programmable 1.8 V to 3.5 V Output Voltage Dual N-Channel Synchronous Driver Total Output Accuracy 1% (0 C to 70 C) High Efficiency Current-Mode Operation Short Circuit Protection Power Good Output Integrated Overvoltage Protection Crowbar 16-Lead SOIC Package VRM 8.2 Compatible APPLICATIONS Desktop PC Power Supply for: Pentium II Processor Pentium Pro Processor Pentium Processor AMD-K6 Processor VRM Modules
VCC +12V
5-Bit Programmable Synchronous Switching Regulator Controller for Pentium(R) II Processor ADP3152
GENERAL DESCRIPTION
The ADP3152 is a highly efficient synchronous switching regulator controller optimized for Pentium II Processor applications where 5 V is stepped down to a digitally controlled output voltage between 1.8 V and 3.5 V. Using a 5-bit DAC to read a voltage identification (VID) code directly from the processor, the ADP3152 uses a current mode constant off-time architecture to generate its precise output voltage. The ADP3152 drives two N-channel MOSFETS in a synchronous rectified buck converter, at a maximum switching frequency of 250 kHz. Using the recommended loop compensation and guidelines, the ADP3152 provides a dc/dc converter that meets Intel's stringent transient specifications with a minimum number of output capacitors and smallest footprint. Additionally, the current mode architecture also provides guaranteed short circuit protection and adjustable current limiting.
VIN +5V +
22 F
1F VCC SD CMP DRIVE1
CIN
R1
ADP3152
CCOMP 150pF AGND SENSE+ CT
IRL3103
L 2.5 H
RSENSE 6.7m + CO
VO 1.8V-3.5V 14A
R2
1nF SENSE- DRIVE2 IRL3103 PGND VID0-VID4 10BQ015
5-BIT CODE
Figure 1. Typical Application
Pentium is a registered trademark of Intel Corporation. All other trademarks are the property of their respective holders.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
ADP3152-SPECIFICATIONS (0 C T +70 C, V
A
CC
= 12 V, VIN = 5 V, unless otherwise noted)
Min -1.0 -1.0 -1.0 0.05 0.1 3.7 140 125 145 4.5 250 165 0.6 2.0 Typ Max 1.0 1.0 1.0 Units % % % % % mA A mV V V A k A A s ns % % s 24 % k mmho V V kHz 0.6 2.0 10 V V A
Parameter OUTPUT ACCURACY 1.8 V Output Voltage 2.8 V Output Voltage 3.5 V Output Voltage OUTPUT VOLTAGE LINE REGULATION OUTPUT VOLTAGE LOAD REGULATION INPUT DC SUPPLY CURRENT Normal Mode Shutdown
1
Symbol VO
Conditions With Respect to Nominal Output Voltage (Figure 13) ILOAD = 10 A (Figure 2) VIN = 4.75 V to 5.25 V (Figure 2) 200 mA < ILOAD < 14 A VSD = 0.8 V TA = +25C, VID Pins Floating V7 Forced to VOUT - 3%
VO VO
IQ
CURRENT SENSE THRESHOLD VOLTAGE VID PINS THRESHOLD Low High VID PINS INPUT CURRENT VID0-VID4 PULL-UP RESISTANCE CT PIN DISCHARGE CURRENT
V8-V7 V16, V1-V4
I16, I1-I4 RVID I9
VID = 0 V 20 TA = +25C VOUT in Regulation VOUT = 0 V CT = 150 pF CL = 7000 pF (Pins 13, 14) TA = +25C Output Coming Into Regulation Output Coming Into Regulation -8 1.8
110 30 65 2 2.45 120 5 -5 500
220
10 3.2 200 8
OFFTIME DRIVER OUTPUT TRANSITION TIMES POSITIVE POWER GOOD TRIP POINT NEGATIVE POWER GOOD TRIP POINT POWER GOOD RESPONSE TIME CROWBAR TRIP POINT ERROR AMPLIFIER OUTPUT IMPEDANCE ERROR AMPLIFIER TRANSCONDUCTANCE ERROR AMPLIFIER MINIMUM OUTPUT VOLTAGE ERROR AMPLIFIER MAXIMUM OUTPUT VOLTAGE ERROR AMPLIFIER BANDWIDTH -3 dB SHUTDOWN (SD) PIN Low Threshold High Threshold Input Current
tOFF tR, tF VPWRGD VPWRGD tPWRGD VCROWBAR ROERR GMERR VCMPMIN VCMPMAX BWERR SDL SDH SDIB
% Above Output Voltage
9
15 145 2.2
V7 Forced to VOUT + 3% V7 Forced to VOUT - 3% CMP = Open Part Active Part in Shutdown
0.8 2.4 500
NOTES 1 Dynamic supply current is higher due to the gate charge being delivered to the external MOSFETS. All limits at temperature extremes are guaranteed via correlation using standard quality control methods. Specifications are subject to change without notice.
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PIN FUNCTION DESCRIPTIONS
Pin 1-4, 16
Mnemonic VID1-VID4, VD0
Function Voltage Identification DAC Input Pins. These pins are internally pulled up to VREG providing a logic one if left open. Leaving all five DAC inputs open results in placing the ADP3152 into shutdown. Analog Ground Pin. This pin must be routed separately to the (-) terminal of COUT. Shutdown Pin. A logic high will place the ADP3152 in shutdown and disable the output. This pin is internally pulled down. Connects to the internal resistor divider which, along with the VID code, sets the output voltage. Pin 7 is also the (-) input for the current comparator. The (+) input for the current comparator. A threshold between Pins 8 and 7 set by the error amplifier in conjunction with RSENSE, sets the current trip point. External Capacitor CT from Pin 9 to ground sets the off time of the device. Error Amplifier Compensation Point. The current comparator threshold increases with the Pin 10 voltage. Power Good Pin. An open drain signal to indicate that the output voltage is within a 5% regulation band. Input Voltage Pin. Gate Drive for the bottom synchronous N-channel MOSFET. The voltage at Pin 13 swings from ground to VCC. Gate Drive for the top primary N-channel MOSFET. The voltage at Pin 14 swings from ground to VCC. Driver Power Ground. Connects to the source of the bottom N-channel MOSFET and to the (-) terminal of CIN.
PIN CONFIGURATION
VID1 1 VID2 2 VID3 3
4
5 6 7 8 9 10 11 12 13 14 15
AGND SD SENSE- SENSE+ CT CMP PWRGD VCC DRIVE2 DRIVE1 PGND
ABSOLUTE MAXIMUM RATINGS*
Input Supply Voltage (Pin 12) . . . . . . . . . . . . -0.3 V to +16 V VID0-VID4, SD, PWRGD, CMP, CT . . . . . . . -0.3 V to VCC DRIVE1, DRIVE2, SENSE+, SENSE- . . . . . . -0.3 V to VCC Operating Temperature Range . . . . . . . . . . . . . 0C to +70C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150C JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110C/W Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300C
*This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged.
16 15 14
VID0 PGND DRIVE1
DRIVE2 VID4 TOP VIEW AGND 5 (Not to Scale) 12 VCC
13
ADP3152
SD 6 SENSE- 7 SENSE+ 8
11 10 9
PWRGD CMP CT
ORDERING GUIDE
Model ADP3152AR
Temperature Package Range Description 0C to +70C 16-Lead SOIC
Package Option R-16A/SO-16
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3152 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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ADP3152
22 100k 3 2700 F/10V + 22 F P SYSTEM 1 2 3 4 5 6 7 8 + 1F + + + 1F L2 1.7 H VCC + 12V VIN + 5V +5V RTN +12V RTN 16 15 14 13 12 11 10 9 CT 150pF 1nF R2 39k 2nF CCOMP 220 220 R1 150k RTN IRL3103 10BQ015 + + + + + + IRL3103 L1 2.5 H RSENSE 6.7m
ADP3152
VID1 VID2 VID3 VID4 AGND SD SENSE- SENSE+ VID0 PGND DRIVE1 DRIVE2 VCC PWRGD CMP CT
2700 F
6 (10V)
VO 1.8V-3.5V 0-14A
Figure 2. Typical Application for Pentium II
VCC
12
DRIVE1 DRIVE2 PGND AGND
14 13 15 5
PWRGD
11
SENSE+
8
SENSE-
7
VREF + 15% NONOVERLAP DRIVE
DELAY
ADP3152
REFERENCE 2R
SD 6
IN
CROWBAR VREF + 5% VREF - 5% CMPI S Q R VT1 gm CMPT VREF R
1.20V
16
VID0 VID1 VID2 VID3 VID4
1
VT2
2
3
OFF-TIME CONTROL
9
4
SENSE-
DAC
10
CT
CMP
Figure 3. Functional Block Diagram
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Typical Performance Characteristics-ADP3152
100 95 VOUT = +3.5V FREQUENCY - kHz 90 EFFICIENCY - % 85 VOUT = +2.0V 80 75 70 65 1.4 2.8 4.2 5.6 7.0 8.4 9.8 11.2 12.6 14.0 OUTPUT CURRENT - Amps VOUT = +2.8V 450 SEE FIGURE 2 GATE CHARGE CURRENT - mA 400 350 300 250 200 150 100 50 0 50 100 200 300 400 500 600 700 800 TIMING CAPACITOR - pF 40 35 30 25 20 15 10 5 0 45 58 83 134 OPERATING FREQUENCY - kHz 397 Qn + Qn = 100nC 45
Figure 4. Efficiency vs. Output Current
Figure 5. Frequency vs. Timing Capacitor
Figure 6. Gate Charge Supply Current vs. Operating Frequency
SEE FIGURE 2 VOUT = +3.5V, IOUT = 10A PRIMARY N-DRIVE DRIVER OUTPUT
1
SEE FIGURE 2
OUTPUT VOLTAGE 20mV/DIV
SECONDARY N-DRIVE DRIVER OUTPUT
2 2
OUTPUT CURRENT 14A TO 1A
DRIVE 1 AND 2 = 5V/DIV
500ns/DIV
100ns/DIV
10 s/DIV
Figure 7. Gate Switching Waveforms
Figure 8. Driver Transition Waveforms
Figure 9. Transient Response, 14 A-1A of Figure 2 Circuit
25 TA = +25 C SEE FIGURE 13 20 NUMBER OF PARTS
OUTPUT VOLTAGE 20mV/DIV
3
VCC VOLTAGE 5V/DIV
15
10
OUTPUT CURRENT 1A TO 14A
4
REGULATOR OUTPUT VOLTAGE 1V/DIV
5
10ms
Figure 10. Transient Response, 1A-14 A of Figure 2 Circuit
Figure 11. Power-On Start-Up Waveforms
Figure 12. Output Accuracy Distribution, VOUT = 2.8 V
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-0.55 -0.5 -0.45 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
0
OUTPUT ACCURACY - %
ADP3152
12V 5-BIT CODE VID0- VID4 SD CMP 1k CT 4700pF VCC DRIVE1 DRIVE2 SENSE+ SENSE- +
causes an increase in the output of the voltage-error amplifier, which, in turn, leads to an increase in the current comparator threshold VT1, thus tracking the load current.
1F 0.1 F
Table I. Output Voltage vs. VID Code
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
VOUT 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.85 1.90 1.95 2.00 2.05 Shutdown 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.40 3.50
ADP3152
AGND PGND VOUT
100k 1.2V
OP27
0.1 F
Figure 13. Closed-Loop Test Circuit for Accuracy
APPLICATION INFORMATION
The ADP3152 uses a current-mode, constant-off-time control technique to switch a pair of external N-channel MOSFETs in a synchronous rectified buck converter application. Due to the constant-off-time operation, no slope compensation is needed. A unique feature of the constant-off-time control technique is that the converter's frequency becomes a function of the ratio of input voltage to output voltage. The off time is determined by the value of the external capacitor connected to the CT pin. The on time varies in such a way that a regulated output voltage is maintained. The output voltage is sensed by an internal voltage divider that is connected to the Sense- pin. A voltage-error amplifier gm compares the values of the divided output voltage with a reference voltage. The reference voltage is set by an onboard 5-bit DAC, which reads the code present at the voltage identification (VID) pins and converts it to a precise value between 600 mV and 1.167 V. Refer to Table I for the output voltage vs. VID pin code information. During continuous-inductor-current mode of operation, the voltage-error amplifier gm and the current comparator CMPI are the main control elements. During the on time of the high side MOSFET, the current comparator CMPI monitors the voltage between the Sense+ and Sense- pins. When the voltage level between the two pins reaches the threshold level VT1, the high side drive output is switched to zero, which turns off the high side MOSFET. The timing capacitor CT is now discharged at a rate determined by the off time controller. In order to maintain a ripple current in the inductor, which is independent of the output voltage, the discharge current is made proportional to the value of the output voltage (measured at the Sense- pin). While the timing capacitor is discharging, the low side drive output goes high, turning on the low side MOSFET. When the voltage level on the timing capacitor has discharged to the threshold voltage level VT2 , comparator CMPT resets the SR flip-flop. The output of the flip-flop forces the low side drive output to go low and the high side drive output to go high. As a result, the low side switch is turned off and the high side switch is turned on. The sequence is then repeated. As the load current increases, the output voltage starts to decrease. This
To prevent cross conduction of the external MOSFETs, feedback is incorporated to sense the state of the driver output pins. Before the low side drive output can go high, the high side drive output must be low. Likewise, the high side drive output is unable to go high while the low side drive output is high.
Power Good
The ADP3152 has an internal monitor which monitors the output voltage and drives the PWRGD pin of the device. This pin is an open drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage has been within a 5% regulation band of the targeted value for more than 500 s. The PWRGD pin will go low if the output is outside the regulation band for more than 500 s.
Output Crowbar
An added feature of using an N-channel MOSFET as the synchronous switch is the ability to crowbar the output with the same MOSFET. If the output voltage is 15% greater than the desired regulated value, the ADP3152 will turn on the lower MOSFET, which will current-limit the source power supply or blow its fuse, pull down the output voltage, and thus save the
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expensive microprocessor from destruction. The crowbar function releases at approximately 50% of the nominal output voltage. For example, if the output is programmed to 2.0 V, but is pulled up to 2.3 V or above, the crowbar will turn on the lower MOSFET. If in this case the output is pulled down to less than 1.0 V, the crowbar will release, allowing the output voltage to recover to 2.0 V.
Shutdown
The timing capacitor can be calculated from the equation: CT = tOFF x 65 A = 143 pF 1V
The ADP3152 has a shutdown pin which is pulled logic low by an internal resistor. In this condition the device functions normally. This pin should be pulled high externally to disable the output drives.
Calculation of Component Values
The converter operates at the nominal operating frequency only at the above specified VO and at light load. At higher VO, and heavy load, the operating frequency decreases due to the parasitic voltage drops across the power devices. The actual minimum frequency at VO = 2.8 V is calculated to be 160 kHz (see Equation 1 below). Where IIN R IN R DS(ON)HSF R DS(ON)LSF R SENSE RL is the input dc current (assuming an efficiency of 90%, IIN = 9 A) is the resistance of the input filter (estimated value: 7 m) is the resistance of the high side MOSFET (estimated value: 10 m) is the resistance of the low side MOSFET (estimated value: 10 m) is the resistance of the sense resistor (estimated value: 7 m) is the resistance of the inductor (estimated value: 6 m)
The design parameters for a typical 300 MHz Pentium II application (Figure 2) are as follows: Input voltage: VIN = 5 V Auxiliary input: VCC = 12 V Output voltage: VO = 2.8 V Maximum output current: IOMAX = 14.2 Adc Minimum output current: IOMIN = 0.8 Adc Static tolerance of the supply voltage for the processor core: VOST+ = 100 mV VOST- = -60 mV Transient tolerance (for less than 2 s) of the supply voltage for the processor core when the load changes between the minimum and maximum values with a di/dt of 30 A/s: VOTR+ = 130 mV VOTR- = -130 mV Input current di/dt when the load changes between the minimum and maximum values: less than 0.1 A/s The above requirements correspond to Intel's published power supply requirements based on VRM 8.2 guidelines.
C T Selection for Operating Frequency
C O Selection--Determining the ESR
The selection of the output capacitor is driven by the required ESR and capacitance CO. The ESR must be small enough that both the resistive voltage deviation due to a step change in the load current and the output ripple voltage stay below the values defined in the specification of the supplied microprocessor. The capacitance, CO, must be large enough that the output is held up while the inductor current ramps up or down to the value corresponding to the new load current. The total static tolerance of the Pentium II processor is 160 mV. Taking into account the 1% setpoint accuracy of the ADP3152, and assuming a 0.5% (or 14 mV) peak-to-peak ripple, the allowed static voltage deviation of the output voltage when the load changes between the minimum and maximum values is 0.08 V. Assuming a step change of I = IOMAX-IOMIN = 13.4 A, and allocating all of the total allowed static deviation to the contribution of the ESR sets the following limit: RE ( MAX ) = ESRMAX 1 = 0.08 13. 4 = 5.9 m
The ADP3152 uses a constant-off-time architecture with tOFF determined by an external timing capacitor CT. Each time the high side N-channel MOSFET switch turns on, the voltage across CT is reset to approximately 3.3 V. During the off time, CT is discharged by a constant current of 65 A to 2.3 V, that is by 1 V. The value of the off time is calculated from the preferred continuous-mode operating frequency. Assuming a nominal operating frequency of fNOM = 200 kHz at an output voltage of VO = 2.8 V, the corresponding off time is: VO 1 tOFF = 1- = 2.2 s V IN f NOM
f MIN =
1 V IN - I IN RIN - IOMAX (RDS(ON )HSF + RSENSE + RL ) -V O x = 160 kHz tOFF V IN - I IN RIN - IOMAX (RDS(ON )HSF + RSENSE + RL - RDS(ON )LSF )
(1)
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ADP3152
The output filter capacitor must have an ESR of less than 5.9 m. One can use, for example, six FA type capacitors from Panasonic, with 2700 F capacitance, 10 V voltage rating, and 34 m ESR. The six capacitors have a total typical ESR of ~ 5 m when connected in parallel.
Inductor Selection RSENSE
The minimum inductor value can be calculated from ESR, off time, dc output voltage and allowed peak-to-peak ripple voltage. LMIN1 = V OtOFF RE( MAX ) V RIPPLE , p -p = 2.8 x 2.2 x 5.9 m 14 m = 2.6 H
The value of RSENSE is based on the required output current. The current comparator of the ADP3152 has a threshold range that extends from 0 mV to 125 mV (minimum). Note that the full 125 mV range cannot be used for the maximum specified nominal current, as headroom is needed for current ripple, transients and inductor core saturation. The current comparator threshold sets the peak of the inductor current yielding a maximum output current IOMAX, which equals the peak value less half of the peak-to-peak ripple current. Solving for RSENSE and allowing a margin for tolerances inside the ADP3152 and in the external component values yields: RSENSE = (125 mV)/[1.2(IOMAX + IRPP/2)] = 6.8 m A practical solution is to use three 20 m resistors in parallel, with an effective resistance of about 6.7 m. Once RSENSE has been chosen, the peak short-circuit current ISC(PK) can be predicted from the following equation: ISC(PK) = (145 mV)/R SENSE = (145 mV)/(6.7 m) = 21.5 A The actual short-circuit current is less than the above calculated ISC(PK) value because the off time rapidly increases when the output voltage drops below 1 V. The relationship between the off time and the output voltage is: tOFF CT x 1V VO + 2 A 360 k
The minimum inductance gives a peak-to-peak ripple current of 2.15 A, or 15% of the maximum dc output current IOMAX. The inductor peak current in normal operation is: ILPEAK = IOMAX + IRPP /2 = 15.3 A The inductor valley current is: ILVALLEY = ILPEAK - IRPP = 13 A The inductor for this application should have an inductance of 2.6 H at full load current and should not saturate at the worst-case overload or short circuit current at the maximum specified ambient temperature. A suitable inductor is the CTX12-13855 from Coiltronics, which is 4.4 H at 1 A and about 2.5 H at 14.2 A.
Tips for Selecting Inductor Core
Ferrite designs have very low core loss, so the design should focus on copper loss and on preventing saturation. Molypermalloy, or MPP, is a low loss core material for toroids, and it yields the smallest size inductor, but MPP cores are more expensive than ferrite cores or the Kool M(R) cores from Magnetics, Inc. The lowest cost core is made of powdered iron, for example the #52 material from Micrometals, Inc., but yields the largest size inductor.
C O Selection--Determining the Capacitance
The minimum capacitance of the output capacitor is determined from the requirement that the output be held up while the inductor current ramps up (or down) to the new value. The minimum capacitance should produce an initial dv/dt which is equal (but opposite in sign) to the dv/dt obtained by multiplying the di/dt in the inductor and the ESR of the capacitor. CMIN = IOMAX - IOMIN RE (di/dt ) = 14.2 - 0.8 5.9 m (2.2 / 4. 4 H ) = 4.5 mF
With a short across the output, the off time will be about 70 s. During that off time the inductor current gradually decays. The amount of decay depends on the L/R time constant in the output circuit. With an inductance of 2.5 H and total resistance of 23 m, the time constant will be 108 s, which yields a valley current of 11.3 A and an average short-circuit current of about 16.3 A. To safely carry the short-circuit current, the sense resistor must have a power rating of at least 16.3 A2 x 6.8 m = 1.8 W.
Current Transformer Option
In the above equation the value of di/dt is calculated as the smaller voltage across the inductor (i.e., VIN-VO rather than VO) divided by the maximum inductance (4.4 H) of the CTX1213855 inductor from Coiltronics. The parallel-connected six 2700 F/10 V FA series capacitors from Panasonic have a total capacitance of 16,200 F, so the minimum capacitance requirement is met with ample margin.
An alternative to using low value and high power current sense resistor is to reduce the sensed current by using a low cost current transformer and a diode. The current can then be sensed with a small-size, low cost SMT resistor. If we use a transformer with one primary and 50 secondary turns, the worst-case resistor dissipation is reduced to a fraction of a mW. Another advantage of using this option is the separation of the current and voltage sensing, which makes the voltage sensing more accurate.
Power MOSFET
Two external N-channel power MOSFETs must be selected for use with the ADP3152, one for the main switch, and an identical one for the synchronous switch. The main selection parameters for the power MOSFETs are the threshold voltage VGS(TH) and the on resistance RDS(ON).
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ADP3152
The minimum input voltage dictates whether standard threshold or logic-level threshold MOSFETs must be used. For VIN > 8 V, standard threshold MOSFETs (VGS(TH) < 4 V) may be used. If VIN is expected to drop below 8 V, logic-level threshold MOSFETs (VGS(TH) < 2.5 V) are strongly recommended. Only logic-level MOSFETs with VGS ratings higher than the absolute maximum of VCC should be used. The maximum output current IOMAX determines the RDS(ON) requirement for the two power MOSFETs. When the ADP3152 is operating in continuous mode, the simplifying assumption can be made that one of the two MOSFETs is always conducting the average load current. For VIN = 5 V and VO = 2.8 V, the maximum duty ratio of the high side FET is: DMAXHF = (1-fMIN x tOFF) =(1-160 kHz x 2.2 s) = 65% The maximum duty ratio of the low side (synchronous rectifier) FET is: DMAXLF = 1 - DMAXHF = 35% The maximum rms current of the high side FET is: IRMSLS = [DMAXHF (ILVALLEY 2 + ILPEAK2 + ILVALLEY ILPEAK)/3]0.5 = 11.5 Arms The maximum rms current of the low side FET is: IRMSLS = [DMAXLF (ILVALLEY2 + ILPEAK2 + ILVALLEYILPEAK)/3]0.5 = 8.41 Arms The RDS(ON) for each FET can be derived from the allowable dissipation. If we allow 5% of the maximum output power for FET dissipation, the total dissipation will be: PFETALL = 0.05 VO IOMAX = 2 W Allocating two-thirds of the total dissipation for the high side FET and one-third for the low side FET, the required minimum FET resistances will be: RDS(ON)HSF(MIN) = 1.33/11.52 = 10 m RDS(ON)LSF(MIN) = 0.67/8.412 = 9.5 m Note that there is a tradeoff between converter efficiency and cost. Larger FETs reduce the conduction losses and allow higher efficiency but lead to increased cost. If efficiency is not a major concern the Fairchild MOSFET NDP6030L or International Rectifier IRL3103 is an economical choice for both the high side and low side positions. Those devices have an R DS(ON) of 14 m at VGS = 10 V and at 25C. The low side FET is turned on with at least 10 V. The high side FET, however, is turned on with only 12 V - 5 V = 7 V. If we check the typical output characteristics of the device in the data sheet, we find that for an output current of 10 A, and at a VGS of 7 V, the VDS is 0.15 V, which gives a RDS(ON) = VDS/ID = 15 m. This value is only slightly above the one specified at a VGS of 10 V, so the resistance increase due to the reduced gate drive can be neglected. We have to modify, however, the specified RDS(ON) at the expected highest FET junction temperature of 140C by a RDS(ON) multiplier, using the graph in the data sheet. In our case: RDS(ON)MULT = 1.7 Using this multiplier, the expected RDS(ON) at 140C is 1.7 x 14 = 24 m. The high side FET dissipation is: PDFETHS = IRMSHS2RDS(ON) + 0.5 VINILPEAKQG fMAX/IG = 3.72 W where the second term represents the turn-off loss of the FET. (In the second term, QG is the gate charge to be removed from the gate for turn-off and IG is the gate current. From the data sheet, QG is about 50 nC -70 nC and the gate drive current provided by the ADP3152 is about 1 A.) The low side FET dissipation is: PDFETLS = IRMSLS 2R DS(ON) = 1.7 W (Note that there are no switching losses in the low side FET.) To remove the dissipation of the chosen FETs, proper heatsinks should be used. The Thermalloy 6030 heatsink has a thermal impedance of 13C/W with convection cooling. With this heatsink, the junction-to-ambient thermal impedance of the chosen high side FET JAHS will be 13 (heatsink-to-ambient) + 2 (junction-to-case) + 0.5 (case-to-heatsink) = 15.5C/W. At full load and at 50C ambient temperature, the junction temperature of the high side FET is: TJHSMAX = TA + JAHS PDFETHS = 105C A smaller heatsink may be used for the low side FET, e.g., the Thermalloy type 7141 ( = 20.3C/W). With this heatsink, the thermal impedance JALS for the low side FET = 33.8C/W. The low side FET junction temperature is: TJLSMAX = TA + JALS PDFETLS = 106C All of the above calculated junction temperatures are safely below the 175C maximum specified junction temperature of the selected FET. The maximum operating junction temperature of the ADP3152 is calculated as follows: TJICMAX = TA + JA (IICVCC + PDR) where JA is the junction to ambient thermal impedance of the ADP3152 and PDR is the drive power. From the data sheet, JA is equal to 110C/W and IIC = 2.7 mA. PDR can be calculated as follows: PDR = (CRSS + CISS)VCC2 fMAX = 307 mW The result is: TJICMAX = 86C
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ADP3152
C IN Selection and Input Current di/dt Reduction
In continuous-inductor-current mode, the source current of the high side MOSFET is a square wave with a duty ratio of VO/ VIN. To keep the input ripple voltage at a low value, one or more capacitors with low equivalent series resistance (ESR) and adequate ripple-current rating must be connected across the input terminals. The maximum rms current of the input bypass capacitors is: ICINRMS [VO (VIN - VO)]0.5 IOMAX /VIN = 7 Arms Let us select the FA-type capacitor with 2700 F capacitance and 10 V voltage rating. The ESR of that capacitor is 34 m and the allowed ripple current at 100 kHz is 1.94 A. At 105C we would need to connect at least four such capacitors in parallel to handle the calculated ripple current. At 50C ambient, however, the ripple current can be increased, so three capacitors in parallel are adequate. The ripple voltage across the three paralleled capacitors is: VCINRPL = IOMAX [ESRIN /3 + DMAXHF /(3CIN fMIN )] 140 mV p-p To further reduce the effect of the ripple voltage on the system supply voltage bus and to reduce the input-current di/dt to below the recommended maximum of 0.1 A/s, an additional small inductor (L > 1.7 H @ 10 A) should be inserted between the converter and the supply bus (see Figure 2).
Feedback Loop Compensation Design
In the application circuit we tested, we found that the compensation scheme shown in Figure 2 gave the optimal response to meet the Pentium II dc/dc static and transient specifications with sufficient margins including the ADP3152's initial error tolerance, the PCB layout trace resistances, and the external component parasitics. If we increase the load resistance to the COMP pin, the static regulation will improve. The load transient response, however, will get worse. In Figure 2, if we decrease the R1 = 150 k resistor vs. the R2 = 39 k resistor, the regulation band will shift positive in relation to the 2.8 V. If we increase the R1 resistor, the regulation band will shift negative. It may be necessary to adjust these resistor values to obtain the best static and dynamic regulation compliance depending on the output capacitor ESR and the parasitic trace resistances of the PCB layout.
BOARD LAYOUT
A multilayer PCB is recommended with a minimum of two copper layers. One layer on top should be used for traces interconnecting low power SMT components. The ground terminals of those components should be connected with vias to the bottom traces connecting directly to the ADP3152 ground pins. One layer should be a power ground plane. If four layers are possible, one additional layer should be an internal system ground plane, and one additional layer can be used for other system interconnections. When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ADP3152. It is advisable to follow the evaluation board layout as closely as possible. If necessary, contact Analog Devices Application Engineering for layout suggestions.
To keep the peak-to-peak output voltage deviation as small as possible, the low frequency output impedance (i.e., the output resistance) of the converter should be made equal to the ESR of the output capacitor. That can be achieved by having a single-pole roll-off of the voltage gain of the gm error amplifier, where the pole frequency coincides with the ESR zero of the output capacitor. A gain with single-pole roll-off requires that the gm amplifier is terminated by the parallel combination of a resistor and capacitor. The required resistor value can be calculated from the equation: g m 145 k RCOMP
(
36 x RSENSE
)
= RE
where gm = 2.2 ms and the quantities 36 and 145 k are characteristic of the ADP3152. The calculated compensating resistance is: R1 R2 = RCOMP = 31 k The compensating capacitance is determined from the equality of the pole frequency of the error amplifier gain and the zero frequency of the impedance of the output capacitor. CCOMP = RE COUT RCOMP = 5 m x 16.2 mF 31 k = 2.6 nF
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ADP3152
Board Layout Guidelines
1. The power loop should be routed on the PCB to encompass small areas to minimize radiated switching noise energy to the control circuit and thus to avoid circuit problems caused by noise. This technique also helps to reduce radiated EMI. The power loop includes the input capacitors, the two MOSFETs, the sense resistor, the inductor, and the output capacitors. The ground terminals of the input capacitors, the low side FET, the ADP3152, and the output capacitors should be connected together with short and wide traces. It is best to use an internal ground plane. 2. The PGND (power ground) pin of the ADP3152 must return to the grounded terminals of the input and output capacitors and to the source of the low side MOSFET with the shortest and widest traces possible. The AGND (analog ground) pin has to be connected to the ground terminals of the timing capacitor and the compensating capacitor, again with the shortest leads possible, and before it is connected to the PGND pin. 3. The positive terminal of the input capacitors must be connected to the drain of the high side MOSFET. The source terminal of this FET is connected to the drain of the low side FET, (whose source is connected to the ground plane direct) with the widest and shortest traces possible. To kill parasitic ringing at the input of the buck inductor due to parasitic capacitances and inductances, a small (L >3 mm) ferrite bead is recommended to be placed in the drain lead of the low side FET. Also, to minimize dissipation of the high side
FET, a low voltage 1 A Schottky diode can be connected between the input of the buck inductor and the source of the low side FET. 4. The positive terminal of the bypass capacitors of the +12 V supply must be connected to the VIN pin of the ADP3152 with the shortest leads possible. The negative terminals must be connected to the PGND pin of the ADP3152. 5. The sense pins of the ADP3152 must be connected to the sense resistor with as short traces as possible. Make sure that the two sense traces are routed together with minimum separation (<1 mm). The output side of the sense resistor should be connected to the VCC pin(s) of the CPU with as short and wide PCB traces as possible to reduce the VCC voltage drop. (Each square unit of 1 ounce Cu-trace has a resistance of ~0.53 m. At 14 A, each m of PCB trace resistance between current sense resistor output and VCC terminal(s) of the CPU will reduce the regulated output voltage by 14 mV. The filter capacitors to ground at the sense terminals of the IC should be as close as possible (<8 mm) to the ADP3152. The common ground of the optional filter capacitors should be connected to the AGND pin of the ADP3152 with the shortest traces possible (<10 mm). 6. The microprocessor load should be connected to the output terminals of the converter with the widest and shortest traces possible. Use overlapping traces in different layers to minimize interconnection inductance.
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ADP3152
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead SOIC (R-16A/SO-16)
0.3937 (10.00) 0.3859 (9.80)
16 9 8
0.1574 (4.00) 0.1497 (3.80) 1
0.2440 (6.20) 0.2284 (5.80)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
0.0500 SEATING (1.27) PLANE BSC
0.0192 (0.49) 0.0138 (0.35)
0.0099 (0.25) 0.0075 (0.19)
8 0 0.0500 (1.27) 0.0160 (0.41)
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PRINTED IN U.S.A.
C3260-8-4/98

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